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Designing the computational architecture of the future

As part of a recently announced national microelectronics research program, an ASU team will create a conceptual framework, software tools and integrated circuit examples for new, more power-efficient and capable computer processing architectures. Photo: Marco-Alexis Chaira/ASU
As part of a recently announced national microelectronics research program, an ASU team will create a conceptual framework, software tools and integrated circuit examples for new, more power-efficient and capable computer processing architectures. Photo: Marco-Alexis Chaira/ASU
July 24, 2018
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An Arizona State University research team seeks to create a new framework for designing and building advanced computing platforms that will circumvent the power constraints that exist in a growing range of technologies.

Under the new Electronics Resurgence Initiative (ERI) research program, improved processing capabilities will enable sophisticated applications to operate more effectively in technologies like those that control unmanned aerial vehicles and the internet of things, as well as consumer electronics such as cell phones, cameras and health monitoring devices.

ERI is a multi-year program administered by the U.S. Department of Defense’s Defense Advanced Research Projects Agency (DARPA).

Aspirations to achieve broader technological capabilities are constrained by the limits of current computing technologies, says Daniel Bliss, an associate professor of electrical, computer and energy engineering at ASU.

“I am always computation hungry. I’m interested in taking steps forward on a lot of advanced communications, radar and medical systems, but I never have the computational ability I need,” says Bliss, a systems engineer.

Bliss is leading the Domain-Focused Advanced Software-Reconfiguration Heterogeneous (DASH) portion of the Domain-Specific System on Chip (DSSoC) program, one of one of many research efforts under ERI. The project aligns precisely with the aims of ASU’s Center for Wireless Information Systems and Computational Architectures (WISCA), which Bliss directs.

The assignment is to build a new framework to push development of the next generation of high-performance, embedded, heterogeneous computer processors that are more capable, more power efficient and easier to use, according to Bliss.

The initiative’s directives “are all about exactly what we want to do,” Bliss says. “The bottom line is to help satisfy that hunger for greater computational power that is required by sophisticated signal processing applications.”

Heterogeneous processing boosts performance and energy efficiency on a single, integrated circuit by using multiple types of processors with specialized capabilities to perform specific computing tasks. Because heterogeneous processors are notoriously difficult to program, the WISCA team’s objective is to provide software tools and on-chip intelligence to dramatically simplify implementation.

A key part of DARPA’s objective is to engage the electronics industry and commercial enterprises in the ERI research projects. So Bliss and his ASU team will be working not only with fellow researchers at Carnegie Mellon University, the University of Arizona and the University of Michigan, but also with Arm Limited, EpiSys Sciences Inc., and General Dynamics Mission Systems.

“We are going to go all the way from providing ideas for making it easier to figure out how this new kind of chip should be assembled to providing the software to help put it together,” Bliss explains. “Then we will give you the software and analysis tools to help you program these chips to run multiple applications, including some tools that run in real-time inside the chip,” he adds. 

Moreover, the team hopes to embed intelligent and machine learning functionality into the chips.

“This enables the chip itself to learn, based on how it is being used, so that it can operate more efficiently in the way it is running various applications,” Bliss says.

Beyond those enhanced capabilities, processors using these chips will be capable of running extensive, sophisticated computations with significantly less power – reducing operations that now take hundreds of watts of electrical power to only several watts.

Other research teams working under ERI are integrating different materials into computer processors, enhancing the underlying physics involved in processing and developing novel microelectronics designs and potential new applications. These efforts combined could alter the paradigms of how computer processing is done or even fundamentally change the technology used to do processing, Bliss says.

Unmanned autonomous systems are among the newer technologies that rely heavily on signal processing. But they present a challenge, Bliss says, because “they have limited energy availability, which limits capabilities given current computational systems.”

In addition, the ASU team plans to develop tools that design and use heterogeneous computing processors for signal processing applications, which will improve high-performance communications, sensing and radar technologies, as well as biomedical and health assessment devices.

 “It will affect the technology that lives in cell phones, in your smartwatch, in your camera, the information systems in your car,” Bliss says, “and it could make all of this tech less expensive, more energy efficient and more powerful.

“What should come out of this are better processors for all kinds of things we use in our everyday lives.”

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Theresa Grant

Sr. Media Relations Officer
Beats: Ira A. Fulton Schools of Engineering